1. Field of the Invention
This invention relates to a novel semiconductor resin package structure used for logic LSI in the central processing unit of extra-large computers etc.
2. Description of the Prior Art
Recently there is a tendency that it is required to increase the number of terminals and it is thought that the flip-chip is promising as an LSI system responding thereto. The flip-chip method is one, by which a glass film is formed on the surface of a semiconductor chip of LSI after having finished wiring therein, and electrodes are taken out through holes formed therein and has features that it is possible to take out a number of terminals and that the wiring may be short. In the case where LSIs are mounted on a multi-layer substrate, it is a problem whether it is easy or not to exchange chips in the contact portion between the semiconductor chips and the multi-layer substrate because of the difference between the thermal expansion coefficient of the semiconductor chips and that of the multi-layer substrate. In general, the thermal expansion coefficient of the multi-layer substrate is greater than that of the semiconductor chips and stress is concentrated in the solder in the contact portion connecting the semiconductor chips with the multi-layer substrate because of the difference between the thermal expansion of the semiconductor chips and that of the multi-layer substrate due to heat production during use of the semiconductor chips, and this gives rise to strain therein and destroys the solder. This problem becomes more remarkable, specifically when the semiconductor chips are made larger and their packing density is increased. Further, in the production of apparatuses using LSIs, a semiconductor chip of LSI is connected with a substrate for inspection and reconnected with a multi-layer substrate after its inspection. In this case it may happen often that deficiencies are found in the LSI during the inspection after the connection of the semiconductor chip with the multi-layer substrate and that it is necessary to exchange semiconductor chips of LSI. Furthermore, after the apparatuses have been delivered to a user, it may become necessary to exchange semiconductor chips. Since, in the LSI according to the flip-chip method, the electrodes and solders on the surface of the chip are formed by evaporation, once they are soldered, damage is remarkable, when they are disconnected and soldered again, and thus it is extremely difficult to repeat the reforming of the solder. Further, if the chip is exposed to the atmosphere after the connection, the reforming of the solder is difficult because of the sticking of dust, etc. also it is difficult to secure a certain amount of solder by evaporation.
Heretofore a structure, by which a semiconductor chip having the flip-chip structure is cooled from the rear side, has been proposed in Japanese Patent Examined Publication No. 56-31743. For this structure, metallization is made on the rear surface of the semiconductor chip and this rear surface is adhered on a cooling stud. Although the cooling effect obtained by the flip-chip method is sufficient, in the case where large sized chips are used, there is a problem that their life is shortened by thermal fatigue due to the difference between the thermal expansion coefficient of the chips and that of the multi-layer substrate. For example, when a semiconductor chip of 5 mm square (the distance between the outermost solder bumps is 6.5 mm) is connected on an Al.sub.2 O.sub.3 substrate, whose thermal expansion coefficient .alpha. is 6.8.times.10.sup.-6 /.degree.C., by the flip-chip method, a number of cycles of 1000 is the limit for maintaining the chip structure to be normal during a temperature-cycle acceleration test of 1 hour per cycle (1 h/.infin.) at a temperature range between -55.degree. and 150.degree. C. In the case where the size of the chips is increased, the number of cycles is considerably reduced. That is, the life of the chip structure is remarkably shortened, and this gives rise to a problem in practice. With increasing capacity and speed-up of the computer the number of logic gates formed on a semiconductor chip increases and its wiring pitch becomes smaller or dense. At the same time it is required to mount large size chips of about 10 mm square having an output power higher than 20 W/chip and to realize a mounting method for mounting large sized flip-chips on a multi-layer substrate with a high reliability. However, the flip-chip structure disclosed in Japanese Patent Examined Publication No. 56-31743 doesn't fulfill this requirement. In addition, it is difficult to change the connection of the semiconductor chips with the multi-layer substrate and therefore the flip-chip structure lacks the facility of chip repair (dismounting and reconnection).
In Japanese Patent Unexamined Publication No. 59-996 it has been proposed a connection structure of the substrate for alleviating stress concentration to the solder bump in the connection portion and strain in the solder bump due to the difference between the thermal expansion coefficient of the chips and that of the substrate, in the case where the semiconductor chips are connected with a circuit substrate, where an intermediate substrate, whose thermal expansion coefficient is greater than that of the semiconductor chips and smaller than that of the substrate made of a substance belonging to the Al.sub.2 O.sub.3 family, is disposed between the semiconductor chips and the multi-layer substrate made of a substance belonging to the Al.sub.2 O.sub.3 family, and the semiconductor chips and the intermediate substrate as well as the intermediate substrate and the multi-layer substrate are connected by soldering, respectively so that the stress concentration and the strain produced by heat are dispersed between the semiconductor chips and the intermediate substrate and also between the intermediate substrate and the multi-layer substrate. However, the problem of the stress and strain still remains for this structure and reconnection of the semiconductor chips is not taken into consideration. It is supposed that a plurality of semiconductor chips are connected with the intermediate substrate. Therefore, there is another problem that, when exchange of semiconductor chips is effected for every intermediate substrate, it is necessary to exchange a plurality of semiconductor chips in order to exchange one semiconductor chip, and this raises the cost. Furthermore, it is supposed that the semiconductor chips are exposed to the atmosphere after the connection of the semiconductor chips. With this respect also it is difficult to reconnect the semiconductor chips.
In Japanese Patent Unexamined Publication No. 60-63951 it has been proposed a semiconductor device, in which, when semiconductor chips are connected with solder to a substrate made of epoxy resin, etc., the gap between the semiconductor chips and the substrate is filled with resin having a thermal expansion coefficient, which is approximately equal to that of the solder, which resin surrounds also the semiconductor chips, and in this way stress and strain due to the difference between the thermal expansion coefficient of the semiconductor chips and that of the substrate are dispersed by the resin so that stress applied to the solder bump and strain therein are dispersed. Here it is possible to reduce remarkably stress applied to the solder bump and strain therein. However, it is not possible to reconnect the semiconductor chips and when either one of the semiconductor chips should be replaced by another, after having once connected a plurality of semiconductor chips with the substrate, it is necessary to replace them for every substrate.